Design Verification Engineer
Design Verification Engineer
OpenAI
OpenAI is seeking experienced Design Verification Engineers to join its Hardware organization, which focuses on developing custom silicon for advanced AI workloads. The role involves verifying complex hardware systems and ensuring the functional correctness of AI-native silicon. Candidates will work closely with architecture, RTL, software, and systems teams to deliver reliable silicon at scale.
Qualification
- BS/MS in EE/CE/CS or equivalent with 3+ years of experience in hardware verification.
- Proven success verifying complex IP or SoC designs in industry-standard flows.
- Proficient in SystemVerilog, UVM, and common simulation and debug tools (e.g., VCS, Questa, Verdi).
- Strong knowledge of computer architecture concepts, memory and cache systems, coherency, interconnects, and/or ML compute primitives.
- Familiarity with performance modeling, formal verification, or emulation is a plus.
- Experience working in fast-paced, cross-disciplinary teams with a passion for building reliable hardware.
Responsibility
- Own the verification of custom IP blocks, subsystems, or full-chip SoC-level functionality.
- Define verification plans based on architecture and microarchitecture specs.
- Develop constrained-random, directed, and system-level testbenches using SystemVerilog/UVM or equivalent methodologies.
- Build and maintain stimulus generators, checkers, monitors, and scoreboards to ensure high coverage and correctness.
- Drive bug triage, root cause analysis, and collaborate with design teams on resolution.
- Contribute to regression infrastructure, coverage analysis, and closure for both block- and top-level environments.
